In general, designing high-speed interconnect network structures poses a considerable power challenge as data rates scale to support higher-performance computing systems, both in the server and workstation/desktop space. Indeed, although data rate demands are currently increasing about 2×˜3× annually, improvements in link technology only yield about 20% annual reduction in link power consumption. An important building block in serial communication interconnect architectures is an equalizer, which is used to compensate for channel losses and imperfections caused by various physical effects such as the skin effect, dielectric loss, and reflections due to impedance discontinuities (such as via stubs). In the time domain, these channel losses and impairments can lead to broadening of transmitted pules over more than one unit interval (UI), whereby a received signal can suffer from intersymbol interference (ISI)
A decision feedback equalizer (DFE) is one type of receiver-side equalizer that is commonly employed in high-speed serial communications to compensate for the signal distortions that occur when fast digital pulses are transferred over electrical channels with limited bandwidth. A fundamental advantage of a DFE over a linear equalizer (such as a peaking amplifier) is that a DFE can flatten the channel response (and reduce signal distortion) without amplifying noise or crosstalk and, thus, equalize a channel without noise enhancement.
In general, a DFE uses the decision about the value of the current bit to predict its contribution to intersymbol interference (ISI) produced by channel loss. This prediction is then used to cancel the ISI's effects on subsequent bits via a sum of weighted coefficients (“taps”). More specifically, in a DFE, the previously decided bits are fed back with weighted tap coefficients and added to the received input signal. For an M-tap DFE, the feedback taps are denoted H1, H2, . . . , HM. The H1 tap represents the intersymbol interference (ISI) contributed by a data bit one unit interval (UI) earlier than the current bit being detected, the H2 tap represents the ISI contributed by a data bit two UIs earlier than the current bit, and so on. If the magnitudes and polarities of the tap weights are properly adjusted to match the channel characteristics, the ISI from the previous bits in the data stream will be cancelled, and the bits can be detected by a decision-making latch with a low BER (bit error rate).
As the data rates increase, however, the number of taps required to successfully equalize a channel increases accordingly. This constitutes a major barrier to data rate scaling, since each tap requires dedicated hardware and adds to the loading at a summation node, which is part of the critical timing path.